The invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor.
Complementary-metal-oxide-semiconductor processes may be used to build a combination of p-type and n-type field-effect transistors that are used to construct, for example, logic cells. Field-effect transistors generally include a channel region, a source, a drain, and a gate electrode. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and drain to produce a device output current.
Field-effect transistors fabricated using semiconductor-on-insulator technologies may exhibit certain performance improvements in comparison with comparable field-effect transistors built directly in a bulk silicon substrate. Generally, a silicon-on-insulator (SOI) wafer includes a thin device layer of semiconductor material, a substrate, and a thin buried insulator layer, such as a buried oxide layer, physically separating and electrically isolating the device layer from the substrate. Contingent on the thickness of the device layer, a field-effect transistor may operate in a fully-depleted mode (FDSOI) in which the channel region reaches fully across the device layer to the buried insulator layer when typical control voltages are applied to the gate electrode.
In certain instances, the device layer and buried insulator layer may be removed to expose the substrate over a hybrid region of the SOI wafer and a field-effect transistor may be fabricated using the exposed substrate in the hybrid region. Due to the localized removal of the device layer and buried insulator layer, the field-effect transistor in the hybrid region is recessed in elevation relative to field-effect transistors formed using the device layer. This elevation differential may lead to difficulties when etching openings for contacts in an overlying interlayer dielectric layer. Specifically, during the overetch, unbalanced etch loading can locally widen the shallower contact openings proximate to the source/drain regions of the field-effect transistors formed using the device layer, which may eventually lead to shorting or premature dielectric breakdowns.
Improved structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor are needed.